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Analysis and design of a tri-level current-steering DAC with 12-bit linearity and improved impedance matching suitable for CT-ADCs

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dc.contributor.author Mehta, Shantanu
dc.contributor.author O'Hare, Daniel
dc.contributor.author O'Brien, Vincent
dc.contributor.author Thompson, Eric
dc.contributor.author Mullane, Brendan
dc.date.accessioned 2020-06-19T10:36:03Z
dc.date.available 2020-06-19T10:36:03Z
dc.date.issued 2020
dc.identifier.citation S. Mehta, D. O'Hare, V. O'Brien, E. Thompson, B. Mullane (2020) 'Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs' IEEE Open Journal of Circuits and Systems, 1 (NULL) :34-47. en_US
dc.identifier.issn 2644-1225
dc.identifier.uri http://hdl.handle.net/10344/8941
dc.description peer-reviewed en_US
dc.description.abstract This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysis, we propose a tri-level DAC design that achieves 12-bit static linearity and is suitable for implementation in a continuous-time ADC architecture. To reduce output-impedance related distortion, the design combines DAC slice impedance matching with a proposed compensation technique. By incorporating the tri-level DAC in a continuous-time ADC architecture, the technique demonstrates ~ 8dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology. en_US
dc.language.iso eng en_US
dc.publisher IEEE Computer Society en_US
dc.relation.ispartofseries IEEE Open Journal of Circuits and Systems;1, pp. 34-47
dc.subject topology en_US
dc.subject linearity en_US
dc.subject thermal noise en_US
dc.subject distortion en_US
dc.subject computer architecture en_US
dc.subject simulation en_US
dc.title Analysis and design of a tri-level current-steering DAC with 12-bit linearity and improved impedance matching suitable for CT-ADCs en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2020-06-18T15:23:36Z
dc.description.version PUBLISHED
dc.identifier.doi 10.1109/OJCAS.2020.2994838
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 2957905
dc.internal.copyrightchecked Yes
dc.identifier.journaltitle IEEE Open Journal of Circuits and Systems
dc.description.status Peer reviewed


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