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A tri-level current-steering DAC design with improved output-impedance related dynamic performance

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dc.contributor.author Mehta, Shantanu
dc.contributor.author Scanlan, Anthony G.
dc.contributor.author Mullane, Brendan
dc.contributor.author O'Hare, Daniel
dc.date.accessioned 2020-01-30T09:51:07Z
dc.date.available 2020-01-30T09:51:07Z
dc.date.issued 2020
dc.identifier.citation Shantanu Mehta ; Anthony G. Scanlan ; Brendan Mullane ; Daniel O'Hare (2020) A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Munich, Germany, en_US
dc.identifier.uri http://hdl.handle.net/10344/8452
dc.description peer-reviewed en_US
dc.description.abstract This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology. en_US
dc.language.iso eng en_US
dc.publisher IEEE Computer Society en_US
dc.relation 13RC2077 en_US
dc.relation.ispartofseries 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS);
dc.relation.uri http://dx.doi.org/10.1109/NEWCAS44328.2019.8961257
dc.rights © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en_US
dc.subject HD3 en_US
dc.subject Tri-level en_US
dc.subject current-steering en_US
dc.title A tri-level current-steering DAC design with improved output-impedance related dynamic performance en_US
dc.type info:eu-repo/semantics/conferenceObject en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2020-01-29T11:51:47Z
dc.identifier.doi https://ieeexplore.ieee.org/document/8961257
dc.identifier.doi 10.1109/NEWCAS44328.2019.8961257
dc.contributor.sponsor SFI en_US
dc.contributor.sponsor EI en_US
dc.relation.projectid 13RC2077 en_US
dc.relation.projectid 2014-0293 en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 2942234
dc.internal.rssid 2959326
dc.internal.copyrightchecked Yes
dc.description.status peer-reviewed


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