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Hardware considerations for tensor implementation and analysis using the field programmable gate array

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dc.contributor.author Grout, Ian
dc.contributor.author Mullin, Lenore
dc.date.accessioned 2018-11-29T12:10:12Z
dc.date.available 2018-11-29T12:10:12Z
dc.date.issued 2018
dc.identifier.uri http://hdl.handle.net/10344/7368
dc.description peer-reviewed en_US
dc.description.abstract In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems. en_US
dc.language.iso eng en_US
dc.publisher MDPI en_US
dc.relation.ispartofseries Electronics;7, 320
dc.relation.uri http://dx.doi.org/10.3390/electronics7110320
dc.subject inner and outer product en_US
dc.subject tensor en_US
dc.subject FPGA en_US
dc.subject hardware en_US
dc.title Hardware considerations for tensor implementation and analysis using the field programmable gate array en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.identifier.doi 10.3390/electronics7110320
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US


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