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Modeling the effect of nonideal reference clocks on the jitter generated in timing transfer

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Show simple item record Walker, Jacqueline Cantoni, Antonio 2018-04-18T14:38:10Z 2018-04-18T14:38:10Z 2007
dc.identifier.issn 0090-6778
dc.description peer-reviewed en_US
dc.description.abstract In constant bit-rate timing transfer, the reference clocks which encode and reconstruct the service clock at origin and destination may be jittered. We present new, straightforward approaches to finding and visualizing jitter spectra in timing transfer for jittered destination and reference clocks; and confirm our results by simulation. en_US
dc.language.iso eng en_US
dc.publisher IEEE Computer Society en_US
dc.relation.ispartofseries IEEE Transactions on Communications;55 (1), pp. 44-47
dc.rights © 2007 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en_US
dc.subject synchronization en_US
dc.subject non-uniform sampling en_US
dc.subject jitter en_US
dc.subject SRTS en_US
dc.subject sigma-delta modulator en_US
dc.title Modeling the effect of nonideal reference clocks on the jitter generated in timing transfer en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US 2018-04-18T14:30:33Z
dc.identifier.doi 10.1109/TCOMM.2006.884819
dc.identifier.doi 10.1109/TCOMM.2006.884819
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 1130544
dc.internal.copyrightchecked Yes
dc.description.status peer-reviewed

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