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A FPGA test platform for data converters

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dc.contributor.advisor Mullane, Brendan
dc.contributor.advisor MacNamee, Ciaran
dc.contributor.author Venkatesh, Karra
dc.date.accessioned 2018-02-16T15:50:57Z
dc.date.available 2018-02-16T15:50:57Z
dc.date.issued 2017
dc.identifier.uri http://hdl.handle.net/10344/6573
dc.description peer-reviewed en_US
dc.description.abstract Data converters are used in mixed-signal designs and are important electronic devices with applications in many areas like consumer electronics, communications, computing, control and instrumentation. Design of these data converters to high performance is a challenging task whereas testing of these data converters for correct functionality has also got equal importance. The aim of this thesis is to develop a method for testing data converters using Verilog HDL code and to implement a platform design on a FPGA board. This platform uses the Fast Fourier Transforms as a spectral analysis method for determining the dynamic performance of data converters and associated logic. A focus of attention is to understand the fundamentals of digital signal processing and digital design using good Verilog HDL coding practice. This is achieved through the design and application of a 7-tap FIR filter both in MATLAB and Verilog RTL. This design system is achieved by developing an FPGA test platform using a Xilinx Zynq board FPGA which supports a 1M Sample ADC along with an Analog Mixed Signal card containing external Digital to Analog converters for signal generation. The FPGA supports a sine wave generator that uses sine wave signals as test vectors that are fed to DAC so that an analogue signal is provided to the ADC. The output samples are sampled by the ADC and stored in memory that is then accessed through a serial to parallel interface for spectral analysis in MATLAB. This design is furthered with development of a potential application where the ADC outputs are applied to Finite Impulse Response filters for further analysis. The final results of this thesis include FFT plots and also simulated timing diagrams. en_US
dc.language.iso eng en_US
dc.publisher University of Limerick en_US
dc.subject data converters en_US
dc.subject consumer electronics en_US
dc.subject communication en_US
dc.title A FPGA test platform for data converters en_US
dc.type info:eu-repo/semantics/masterThesis en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.type.supercollection ul_theses_dissertations en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US


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