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A reduced hardware ISI and mismatch shaping DEM decoder

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dc.contributor.author O'Brien, Vincent
dc.contributor.author Scanlan, Anthony G.
dc.contributor.author Mullane, Brendan
dc.date.accessioned 2017-10-31T13:02:04Z
dc.date.issued 2017
dc.identifier.issn 1531-5878
dc.identifier.uri http://hdl.handle.net/10344/6210
dc.description peer-reviewed en_US
dc.description.abstract This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented. en_US
dc.language.iso eng en_US
dc.publisher Springer en_US
dc.relation.ispartofseries Circuits Systems and Signal Processing; 37 (6), pp. 2299-2317
dc.relation.uri http://dx.doi.org/10.1007/s00034-017-0681-8
dc.rights The original publication is available at www.springerlink.com en_US
dc.subject Delta sigma Digital-to-analog converter (DAC) en_US
dc.subject Dynamic element matching (DEM) en_US
dc.subject Element selection logic (ESL) en_US
dc.subject Element selection logic (ESL) en_US
dc.title A reduced hardware ISI and mismatch shaping DEM decoder en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2017-10-31T09:39:56Z
dc.description.version ACCEPTED
dc.identifier.doi 10.1007/s00034-017-0681-8
dc.contributor.sponsor EI en_US
dc.contributor.sponsor ERC en_US
dc.relation.projectid IP/2013/0271 en_US
dc.date.embargoEndDate 2019-10-17
dc.embargo.terms 2019-10-17 en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 2727672
dc.internal.copyrightchecked Yes
dc.identifier.journaltitle Circuits Systems And Signal Processing
dc.description.status peer-reviewed


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