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FPGA-based digital pulse width modulator with optimized linearity

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Show simple item record Scharrer, Martin Josef Halton, Mark Scanlan, Martin 2017-10-18T15:41:38Z 2017-10-18T15:41:38Z 2009
dc.description peer-reviewed en_US
dc.description.abstract This paper proposes a new FPGA based architecture for digital pulse width modulators which takes advantage of dedicated digital clock manager (DCM) blocks present in modern FPGAs and applies manual placement techniques to match internal delays for high linearity. The proposed hybrid DPWM uses a synchronous counterbased coarse-resolution block and a DCM based fine-resolution block implementing a synchronous delay line. The design was successfully implemented on a low-cost Xilinx Spartan-3 FPGA with 9-bit resolution with a switching frequency of 1 MHz. Linearity was manually optimized using the presented technique which reduced the integral non-linearity error by 0.5 LSB. en_US
dc.language.iso eng en_US
dc.publisher IEEE Computer Society en_US
dc.relation.ispartof IEEE Applied Power Electronics Conference and Exposition (APEC) en
dc.relation.ispartofseries Applied Power Electronics Conference and Exposition (APEC);pp. 1220-1225
dc.rights © 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en_US
dc.subject converters en_US
dc.subject resolution en_US
dc.title FPGA-based digital pulse width modulator with optimized linearity en_US
dc.type info:eu-repo/semantics/conferenceObject en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US 2017-10-18T15:34:43Z
dc.description.version ACCEPTED
dc.identifier.doi 10.1109/APEC.2009.4802819
dc.contributor.sponsor EI en_US
dc.relation.projectid CFTD/219/05 en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 1129683
dc.internal.copyrightchecked Yes
dc.description.status peer-reviewed

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