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Hierarchical synthesis system with hybrid DLO-MOGA optimization

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dc.contributor.author Scanlan, Tony
dc.contributor.author Halton, Mark
dc.date.accessioned 2017-10-18T13:52:55Z
dc.date.available 2017-10-18T13:52:55Z
dc.date.issued 2011
dc.identifier.uri http://hdl.handle.net/10344/6174
dc.description peer-reviewed en_US
dc.description.abstract The purpose of this paper is to present a hierarchical circuit synthesis system with a hybrid deterministic local optimization multi-objective genetic algorithm (DLO-MOGA) optimization scheme for system-level synthesis. Design/methodology/approach - The use of a local optimization with a deterministic algorithm based on linear equations which is computationally efficient and improves the feasibility of designs, allows reduction in the number of MOGA generations required to achieve convergence. Findings - This approach reduces the total number of simulation iterations required for optimization. Reduction in run time enables use of full transistor-level models for simulation of critical system-level sub-blocks. Consequently, for system-level synthesis, simulation accuracy is maintained. The approach is demonstrated for the design of pipeline analog-to-digital converters on a 0.35 mu m process. Originality/value - The use of a hybrid DLO-MOGA optimization approach is a new approach to improve hierarchical circuit synthesis time while preserving accuracy. en_US
dc.language.iso eng en_US
dc.publisher Emerald Group Publishing Ltd en_US
dc.relation.ispartofseries Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering;30 (2), pp. 741-761
dc.relation.uri https://doi.org/10.1108/03321641111101186
dc.rights This article is (c) Emerald Group Publishing and permission has been granted for this version to appear here http://ulir.ul.ie. Emerald does not grant permission for this article to be further copied/distributed or hosted elsewhere without the express permission from Emerald en_US
dc.subject programming and algorithm theory en_US
dc.subject systems and control theory en_US
dc.subject control system synthesis en_US
dc.subject design en_US
dc.subject Analog integrated-circuits en_US
dc.title Hierarchical synthesis system with hybrid DLO-MOGA optimization en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2017-10-18T13:42:06Z
dc.description.version ACCEPTED
dc.identifier.doi 10.1108/03321641111101186
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 1129689
dc.internal.copyrightchecked Yes
dc.identifier.journaltitle Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering
dc.description.status peer-reviewed


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