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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications

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dc.contributor.author Rao, Muzaffar
dc.contributor.author Coleman, Joseph
dc.contributor.author Newe, Thomas
dc.date.accessioned 2017-08-21T09:03:15Z
dc.date.available 2017-08-21T09:03:15Z
dc.date.issued 2016
dc.identifier.uri http://hdl.handle.net/10344/6007
dc.description peer-reviewed en_US
dc.description.abstract This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications. en_US
dc.language.iso eng en_US
dc.publisher IEEE Computer Society en_US
dc.relation.ispartof An FPGA Based Reconfigurable IPSec ESP Core suitable for IoT applications en
dc.relation.ispartofseries 2016 10th International Conference on Sensing Technology (ICST);
dc.relation.uri http://dx.doi.org/10.1109/ICSensT.2016.7796269
dc.rights © 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. en_US
dc.subject FPGA en_US
dc.subject AES en_US
dc.subject IPSec en_US
dc.subject ESP en_US
dc.title An FPGA based reconfigurable IPSec ESP core suitable for IoT applications en_US
dc.type info:eu-repo/semantics/conferenceObject en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2017-08-21T08:43:25Z
dc.description.version ACCEPTED
dc.identifier.doi 10.1109/ICSensT.2016.7796269
dc.contributor.sponsor SFI en_US
dc.relation.projectid SFI/12/RC/2302 en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 2698986
dc.internal.copyrightchecked Yes
dc.description.status peer-reviewed


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