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Investigation of a superscalar operand stack using FO4 and ASIC wire-delay metrics

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dc.contributor.author Bailey, Christopher
dc.contributor.author Mullane, Brendan
dc.date.accessioned 2017-03-30T10:55:15Z
dc.date.available 2017-03-30T10:55:15Z
dc.date.issued 2014
dc.identifier.citation Christopher Bailey, Brendan Mullane (2014) 'Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics' VLSI Design, Volume 2014 . en_US
dc.identifier.uri http://hdl.handle.net/10344/5651
dc.description peer-reviewed en_US
dc.description.abstract Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future.This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA).We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics.The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90nm and opportunities for twofold future improvement by using more advanced design approaches. en_US
dc.language.iso eng en_US
dc.publisher Hindawi Publishing Corporation en_US
dc.relation.ispartofseries VLSI Design;Article ID 493189
dc.subject processor microarchitecture en_US
dc.title Investigation of a superscalar operand stack using FO4 and ASIC wire-delay metrics en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2017-03-30T09:28:03Z
dc.description.version PUBLISHED
dc.identifier.doi 10.1155/2014/493189
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 1626772
dc.internal.copyrightchecked Yes
dc.identifier.journaltitle VLSI Design


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