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Analysis of feedback predictive encoder based ADCs

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dc.contributor.author Scanlan, Tony
dc.contributor.author O'Hare, Daniel
dc.contributor.author Halton, Mark
dc.contributor.author O'Brien, Vincent
dc.contributor.author Mullane, Brendan
dc.contributor.author Thompson, Eric
dc.date.accessioned 2017-03-28T07:54:46Z
dc.date.available 2017-03-28T07:54:46Z
dc.date.issued 2017
dc.identifier.citation Scanlan, Anthony and O'Hare, Daniel and Halton, Mark Keith and O'Brien, Vincent and Mullane, Brendan and Thompson, Eric (2017) 'Analysis of feedback predictive encoder based ADCs'. Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering, 36 (1). en_US
dc.identifier.uri http://hdl.handle.net/10344/5644
dc.description peer-reviewed en_US
dc.description.abstract Purpose The purpose of this paper is to present analysis of the feedback predictive encoder based ADC (Analog-to-Digital Converter). Design/methodology/approach The use of feedback predictive encoder based ADCs presents an alternative to the traditional two stage pipeline ADC by replacing the input estimate producing first stage of the pipeline, with a predictive loop that also produces an estimate of the input signal. Findings The overload condition for feedback predictive encoder ADCs is dependent on input signal amplitude and frequency, system gain and filter order. The limitation on the practical useable filter order is set by limit cycle oscillation. A boundary condition is defined for determination of maximum useable filter order. In a practical implementation of the predictive encoder ADC, the time allocated to the key functions of the gain stage and loop quantizer leads to optimisation of the power consumption. Practical implications A practical switched capacitor implementation of the predictive encoder based ADC is proposed. The power consumption of key circuit blocks is investigated. Originality/value This paper presents a methodology to optimise the bandwidth of predictive encoder ADCs. The overload and stability conditions may be used to determine the maximum input signal bandwidth for a given loop quantizer. Optimisation of power consumption based on the allocation of time between the gain stage and the SAR ADC operation is investigated. The lower bound of power consumption for this architecture is estimated. en_US
dc.language.iso eng en_US
dc.publisher Emerald Group Publishing Ltd, en_US
dc.relation.ispartofseries COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering;36 (1), pp. 129-152
dc.relation.uri http://dx.doi.org/10.1108/COMPEL-12-2015-0464
dc.rights This article is (c) Emerald Group Publishing and permission has been granted for this version to appear here http://ulir.ul.ie. Emerald does not grant permission for this article to be further copied/distributed or hosted elsewhere without the express permission from Emerald en_US
dc.subject electronics en_US
dc.subject circuit analysis en_US
dc.subject predictive techniques en_US
dc.subject microelectronics en_US
dc.title Analysis of feedback predictive encoder based ADCs en_US
dc.type info:eu-repo/semantics/article en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.date.updated 2017-03-27T09:08:25Z
dc.description.version ACCEPTED
dc.identifier.doi 10.1108/COMPEL-12-2015-0464
dc.contributor.sponsor EI en_US
dc.contributor.sponsor ERDF en_US
dc.relation.projectid IP-2014-0293 en_US
dc.rights.accessrights info:eu-repo/semantics/openAccess en_US
dc.internal.rssid 2702448
dc.internal.rssid 2702335
dc.internal.copyrightchecked Yes
dc.identifier.journaltitle Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering
dc.description.status peer-reviewed


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