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Modelling e verification language testbenches in UML 2.0 with theme and marte

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Show simple item record Linehan, Eamonn Clarke, Siobhán 2011-07-20T10:36:23Z 2011-07-20T10:36:23Z 2010
dc.description peer-reviewed
dc.description.abstract This document presents a metamodel for the e Hardware Verification Language through example. The e metamodel is captured as a UML 2 profile (UML's mechanism for lightweight extension). Stereotypes from this profile can be used at the modeling level as annotations on models of hardware verification testbenches. This document is organised into sections corresponding to the main constructs of the Hardware Verification Language. For each of these constructs we present: 1) a snippet of code showing their usage; 2) a UML model showing the profile; 3) a sample model annotated with the stereotypes from the profile (corresponding to the code snippet); 4) and an excerpt from the XPAND code generation templates that converts the UML model back into e source code. This document concludes with an overview of the specific extensions to the use of Theme/UML required to accommodate the aspect- oriented constructs in e. en_US
dc.description.sponsorship SFI en_US
dc.language.iso eng en_US
dc.publisher Lero, University of Limerick en_US
dc.relation.ispartofseries Lero Technical Report;Lero-TR-S20P1L0--20020
dc.rights ©2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works
dc.subject hardware verification language en_US
dc.title Modelling e verification language testbenches in UML 2.0 with theme and marte en_US
dc.type Report en_US
dc.type.supercollection all_ul_research en_US
dc.type.restriction none en

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