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Modelling hardware verification concerns specified in the e language: an experience report.

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dc.contributor.author Galpin, Darren
dc.contributor.author Driver, Cormac
dc.contributor.author Clarke, Siobhán
dc.date.accessioned 2012-03-15T14:55:33Z
dc.date.available 2012-03-15T14:55:33Z
dc.date.issued 2009
dc.identifier.uri http://hdl.handle.net/10344/2092
dc.description peer-reviewed en_US
dc.description.abstract e is an aspect-oriented hardware verification language that is widely used to verify the design of electronic circuits through the development and execution of testbenches. In recent years, the continued growth of the testbenches developed at Infineon Technologies has resulted in their becoming difficult to understand, maintain and extend. Consequently, a decision was taken to document the testbenches at a higher level of abstraction. Accordingly, we attempted to model our legacy test suites with an existing aspect-oriented modelling approach. In this paper we describe our experience of applying Theme/UML, an aspectoriented modelling approach, to the representation of aspectoriented testbenches implemented in e. It emerged that the common aspect-oriented concepts supported by Theme/UML were not sufficient to adequately represent the e language, primarily due to e’s dynamic, temporal nature. Based on this experience we propose a number of requirements that must be addressed before aspect-oriented modelling approaches such as Theme/UML are capable of representing aspect-oriented systems implemented in e. en_US
dc.language.iso eng en_US
dc.publisher Association for Computing Machinery en_US
dc.relation.ispartofseries Proceedings of the Internatioanl Conference on Aspect-Oriented Software Development(AOSD) Industry Track;2009
dc.rights "© ACM, 209. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Proceedings of the International Conference on Aspect-Oriented Software Development (AOSD) Industry Track.http://dx.doi.org/10.1145/1509239.1509267 en_US
dc.subject hardware verification en_US
dc.subject aspect-oriented modelling en_US
dc.title Modelling hardware verification concerns specified in the e language: an experience report. en_US
dc.type Conference item en_US
dc.type.supercollection all_ul_research en_US
dc.type.supercollection ul_published_reviewed en_US
dc.type.restriction none en
dc.type.restriction none en
dc.contributor.sponsor SFI
dc.relation.projectid 03/CE2/I303_1

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