| dc.contributor.author | Arshak, Khalil | |
| dc.contributor.author | Jafer, Essa | |
| dc.contributor.author | McDonagh, Declan | |
| dc.date.accessioned | 2011-07-01T16:00:45Z | |
| dc.date.available | 2011-07-01T16:00:45Z | |
| dc.date.issued | 2005 | |
| dc.identifier.uri | http://hdl.handle.net/10344/1065 | |
| dc.description | peer-reviewed | |
| dc.description.abstract | The aim of this study is to model and design an efficient wireless system that should be easy to integrate with other technologies or infrastructures at a low cost. The system is reading analog information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data is converted digitally using ADC and sent to FSK transmitter through FPGA. Verilog HDL has been used to implement the required functions of the FPGA. SIMULINK software has been used to model and simulate Frequency-Shift Keying (FSK) Transmitter/ Receiver suitable for short-range communications. A two-tone FSK signal is generated, passed through a noisy channel, down converted to baseband and passed to FM detector to restore the original transmitted bit stream. The behavioral HDL design has been interfaced to the SIMULINK model and the overall performance has been verified. | en_US |
| dc.description.sponsorship | EI | |
| dc.language.iso | eng | en_US |
| dc.publisher | IEEE Computer Society | en_US |
| dc.relation.ispartofseries | BMAS 2005 - IEEE International Behavioral Modeling and Simulation Conference, 2005; | |
| dc.rights | ©2005 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. | en_US |
| dc.subject | frequency-shift keying | en_US |
| dc.subject | biomedical sensor | en_US |
| dc.title | Modeling remote system for sensor monitoring using Verilog HDL and SIMULINK co-simulation | en_US |
| dc.type | Conference item | en_US |
| dc.type.supercollection | all_ul_research | en_US |
| dc.type.supercollection | ul_published_reviewed | en_US |
| dc.type.restriction | none | en |